1. Field of the Invention
The present invention relates to a high voltage semiconductor device, and, more particularly, to a metal air semiconductor field effect transistor (MASFET) and a method for fabricating the same.
2. Discussion of the Related Art
In a typical metal oxide semiconductor (MOS) device, an oxide film (such as SiO.sub.2) is deposited on a surface of a semiconductor (such as Si), and a metal layer is formed on the oxide film. In a metal oxide semiconductor field effect transistor (MOSFET), a gate insulating film, made of an oxide, and a gate electrode are successively formed on a silicon substrate of a first conductivity type, and source and drain impurity regions are formed beneath the surface of the silicon substrate at both sides of the gate electrode. A MOSFET controls a current (channel current) flowing between the source and drain impurity regions by varying a potential of the gate electrode.
A conventional MOSFET will be described with reference to the accompanying drawings.
FIG. 1 is a plan view of a conventional MOSFET, FIG. 2 is a cross-sectional view taken along line I--I of FIG. 1, FIG. 3 is a cross-sectional view taken along line II--II, and FIGS. 4A to 4D are cross-sectional views showing process steps of manufacturing a conventional MOSFET.
In the construction of a conventional n-channel MOSFET, active and field (i.e. inactive) regions are defined in a P-type semiconductor substrate 1, and a field oxide layer 2 is formed on the semiconductor substrate 1 in a field region (i.e. the inactive region). A gate insulating film 3, a gate electrode 4, and a cap gate insulating film 5 are formed over the active region of the semiconductor substrate 1. Insulating sidewall spacers 7 are formed on sides of the gate insulating layer 3, the gate electrode 4, and the cap gate insulating film. N-type lightly doped impurity regions 6 are formed under the insulating sidewall spacers 7. N-type heavily doped impurity regions 8, which are source and drain regions, are formed at sides of the insulating sidewall spacers 7.
A method for fabricating the conventional MOSFET will be described with reference to FIGS. 4A to 4D. Referring to FIG. 4A, the field oxide layer 2 is formed on the P-type inactive region of the semiconductor substrate 1, and the gate insulating film 3 is formed over an active region of the semiconductor substrate 1.
Referring to FIG. 4B, the gate electrode 4 and the cap gate insulating film 5 are successively formed on a predetermined area of the gate insulating film 3. With the gate electrode 4 and the cap gate insulating film 5 serving as masks, N-type impurity ions are lightly implanted, forming the lightly doped impurity regions 6.
Referring to FIG. 4C, an insulating film is deposited on the structure and is subjected to an anisotropic etch process, forming insulating sidewall spacers 7 which surround the sides of the gate electrode 4 and the cap gate insulating film 5.
Referring to FIG. 4D, with the cap gate insulating film 5 and the insulating sidewall spacers 7 serving as masks, N-type impurity ions are heavily implanted so that the N-type heavily doped impurity regions 8 are formed beneath the surface of the semiconductor substrate 1 at both sides of the sidewall spacers 7.
The operation of the conventional MOSFET will be described below.
When an oxide layer is used as the gate insulating film 3, a channel is formed in the semiconductor substrate 1 under the gate electrode 4 if a voltage higher than a threshold voltage is applied to the gate electrode 4. As a result, current flows between the source and drain regions. A maximum operating voltage the MOSFET is determined by a gate voltage at which the MOSFET can be safely operated for ten years without degradation of its characteristics. A number of stress tests of MOSFET characteristics are known, such as Fowler-Nordheim (FN), SILC (stress induced leakage current), and TDDB (time-dependent dielectric breakdown) of a gate oxide film or drain voltage Vdd satisfying hot carrier life time of a device for ten years.
The conventional MOSFET has a number of problems. First, since N-type lightly doped impurity regions are formed under the insulating sidewall spacers, drain electric field becomes stronger as channel length becomes shorter, and the operational characteristics of the MOSFET depend on gate insulating film properties at an interface between a semiconductor substrate and the gate insulating film, or between insulating sidewall spacers and the semiconductor substrate. Charge traps generated in the gate insulating film or in the insulating sidewall spacer, eventually cause MOSFET devices to malfunction due to dielectric barrier breakdown.
Second, as the gate insulating film becomes thinner, its reliability worsens. The MOSFET cannot be operated at a high voltage since the maximum voltage at which the device can malfunction is close to the maximum gate voltage.